Field of Invention
The present invention relates to a semiconductor device. It particularly relates to a semiconductor device including a main data line that transfers data read from a memory cell array to a main amplifier.
Description of the Related Art
In semiconductor devices, such as DRAM (Dynamic Random Access Memory), the reduction of chip size is important for the reduction of chip unit price. The reduction of chip size in DRAM can be achieved mainly by reducing the size of a memory cell array, and the size reduction percentage in peripheral circuits tends to be lower as compared with the memory cell array. Accordingly, the proportion of peripheral circuits in the entire chip has been increasing year by year, and, in order to further reduce the chip size, it is important to reduce the size of peripheral circuits.
Meanwhile, in synchronous DRAM, for the enhancement of the data transfer rate, attempts have been made to increase the number of prefetches or improve the operation frequency. However, when the number of prefetches is increased, or the operation frequency is improved, the timing margin in data transfer decreases. Thus, a high-precision timing design is required.
Here, it is sometimes difficult to achieve both the size reduction of peripheral circuits and the expansion of the timing margin.
For example, focusing attention on the data transfer between a memory cell array and a main amplifier, when the length of the main data (IO) line that couples the memory cell array and the main amplifier is designed to be short, it becomes unnecessary to couple a sub-amplifier (see Japanese Patent Application Laid Open No. 2011-34645) or the like to the main data line, whereby the timing design is facilitated. However, when the main data line is short, this increases the number of required main amplifiers, and also increases the routing length of a read write bus, resulting in an increase in the circuit scale of peripheral circuits.
Meanwhile, when the length of the main data line is designed to be long, the size of peripheral circuits can be reduced. However, it becomes necessary to control the operation timing of a sub-amplifier, etc., with high precision, making the timing design difficult.
Against the above background, there has been a demand for a semiconductor device that allows peripheral circuits to be reduced in size and also facilitates the timing design.